The present invention relates to a rake architecture employed in CDMA communication systems. More particularly the invention relates to a rake architecture employing a shared memory designed to significantly reduce the memory capacity required and thereby also reduce a die area of an application specific integrated circuit (ASIC) for the rake architecture without any reduction in system capabilities. The architecture may be employed in all types of communication systems employing a rake receiver including, but not limited to, frequency division duplex (FDD), time division duplex (TDD), and time division-synchronous code division multiple access (TD-SCDMA).
Rake receivers are utilized in many types of communications systems. In the wide band code division multiple access (W-CDMA) type of system, a base station transmits primary and secondary sync codes as well as a common pilot channel (CPICH), the pilot signal being unique to each base station. Wireless mobile units (UEs) then receive and synchronize to these codes in order to establish and support a communication.
Referring to FIG. 3, a simplified block diagram of a conventional code tracker 10 is shown. Each rake finger is provided with a code tracker 10. A code generator 12 is provided with a code for a specific base station. The code timing must be offset to compensate for the current time offset from the start of the frame for the assigned peak. An interpolator and decimator filter 14 produces early, late and punctual outputs at 14c, 14b and 14a respectively. The early and late outputs are utilized to keep the punctual output centered in the chip time.
The early, late and punctual outputs are despread with the code for the specific base station at 18, 16 and 20 respectively. The early and late despread signals undergo integration and dumping at integration and dumping devices 22 and 24, squaring at squaring devices 26 and 28 and are summed at 30 to produce an error signal e (t).
FIG. 1 shows the basic timing of a frame. One ten millisecond (10 m sec) synchronization channel (SCH) radio frame is divided into fifteen (15) slots labeled zero (0) through fourteen (14). Each base station transmits a primary sync code and a secondary sync code as well as a common pilot channel (CPICH). Unlike the primary and secondary sync codes that are present only during the first 256 chips of each slot, the CPICH is present during the entire frame and repeats every frame, in addition to being unique for each base station. The rake finger locator uses this uniqueness to perform a correlation against the CPICH from each of the possible base stations in the area of the UE. After the correlation is performed, the rake finger locator determines which peak to assign to which finger of the rake receiver. As was mentioned hereinabove, each UE is typically required to track up to three (3) or more base stations, which capability is due to handover requirements.
Referring to FIG. 3, a simplified block diagram of a conventional code tracker 10 is shown. Each rake finger is provided with a code tracker 10. A code generator 12 is provided with a code for a specific base station. The code timing must be offset to compensate for the current time offset from the start of the frame for the assigned peak. An interpolator and decimator filter 14 produces early, late and punctual outputs at 14c, 14b and 14a respectively. The early and late outputs are utilized to keep the punctual output centered in the chip time.
The early, late and punctual outputs are despread with the code for the specific base station at 18, 16 and 20 respectively. The early and late despread signals undergo integration and dumping at integration and dumping devices 22 and 24, squaring at squaring devices 26 and 28 and are summed at 30 to produce an error signal e (t).
Referring to FIG. 4, a conventional rake structure comprising of six (6) rake fingers is shown. Since all of the rake fingers are substantially identical in design and function, only one is shown in detail in FIG. 4, for purposes of simplicity. As was set forth hereinabove, the code tracker 10 shown in FIG. 3, and also shown in simplified block diagram form in FIG. 4, produces a punctual output 14a (see FIG. 3) which is fed into a delay element 52 which is preferably a circular buffer having a read port and a write port. A memory write pointer 54 increments the memory contents at a chip rate to locations where a punctual input is written and continually points to the next chip location within buffer 52. A read pointer 56 also increments at the chip rate, but is offset from the write pointer 54 based at the number of chips offset from the referenced slot timing. The fine offset is obtained from the code offset circuitry 56 which receives the chip offset at 56a, an output from the code tracker at 56b and the output from code generator 58 at 56c, providing a fine offset for further adjustments of the memory read pointer 56. The buffer 52 provides a time aligned output. It should be understood that the remaining rake fingers “2” through “6” operate in a similar fashion.
FIG. 2 shows a typical multipath. Each of the higher value points represents a multipath.
Each of the punctual outputs is fed into separate time delay elements (not shown) of the rake receiver. The purposes of time delay elements is to remove the time ambiguity, shown in FIG. 2, from the various multipaths. All of the energy remaining after code tracking is then summed in a data estimator (not shown) and is despread and descrambled into symbols.
Referring to FIG. 4, a conventional rake structure comprising of six (6) rake fingers is shown. Since all of the rake fingers are substantially identical in design and function, only one is shown in detail in FIG. 4, for purposes of simplicity. As was set forth hereinabove, the code tracker 10 shown in FIG. 3, and also shown in simplified block diagram form in FIG. 4, produces a punctual output 14a (see FIG. 3) which is fed into a delay element 52 which is preferably a circular buffer having a read port and a write port. A memory write pointer 54 increments the memory contents at a chip rate to locations where a punctual input is written and continually points to the next chip location within buffer 52. A read pointer 56 also increments at the chip rate, but is offset from the write pointer 54 based on the number of chips offsets from the referenced slot timing. The fine offset is obtained from the code offset circuitry 56 which receives the chip offset at 56a, an output from the code tracker at 56b and the output from code generator 58 at 56c, providing a fine offset for further adjustments of the memory read pointer 56. The buffer 52 provides a time aligned output. It should be understood that the remaining rake fingers “2” through “6” operate in a similar fashion.